Publications

(Last update:9/11/2018)
International Conferences & Symposiums
  1. Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, and Shuichi Sakai:
    STRAIGHT: Hazardless Processor Architecture without Register Renaming,
    IEEE/ACM International Symposium on Microarchitecture (MICRO 51), (to appear).

  2. Shinji Sakai, Taishi Suenaga, Ryota Shioya, and Hideki Ando:
    Rearranging Random Issue Queue with High IPC and Short Delay,
    IEEE International Conference on Computer Design (ICCD 36), (to appear).

  3. Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, and Hideki Ando:
    A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode,
    International Conference on Architecture of Computing Systems (ARCS 31) (Springer), (to appear).

  4. Tomoki Tajimi, Anju Hirota, Ryota Shioya, Masahiro Goshima, and Tomoaki Tsumura:
    Initial Study of a Phase-Aware Scheduling for Hardware Transactional Memory,
    IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PacRim), pp. — (2017).

  5. Ryota Shioya, Masahiro Goshima, and Hideki Ando:
    A Front-end Execution Architecture for High Energy Efficiency,
    IEEE/ACM International Symposium on Microarchitecture (MICRO 47), pp. 419—431 (2014).
    DOI: 10.1109/MICRO.2014.35
    [ PDF ] [ SLIDE ]

  6. Ryota Shioya, and Hideki Ando:
    Energy Efficiency Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length,
    IEEE International Conference on Computer Design (ICCD 32), pp. 416—423 (2014).
    DOI: 10.1109/ICCD.2014.6974714
    [ PDF ]

  7. Ryota Shioya, Kazuo Horio, Masahiro Goshima, and Shuichi Sakai:
    Register Cache System not for Latency Reduction Purpose,
    IEEE/ACM International Symposium on Microarchitecture (MICRO 43), pp. 301—312 (2010).
    DOI: 10.1109/MICRO.2010.43
    [ PDF ] [ SLIDE ]

  8. Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, and Shuichi Sakai:
    Low-overhead architecture for security tag,
    IEEE International Symposium on Pacific Rim Dependable Computing (PRDC 2009), pp. 135—142 (2009).
    DOI: 10.1109/PRDC.2009.30

  9. Kunbo Li, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    String-wise information flow tracking against script injection attacks,
    IEEE International Symposium on Pacific Rim Dependable Computing (PRDC 2009), pp. 169—176 (2009).
    DOI: 10.1109/PRDC.2009.35

  10. Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    Base Address Recognition with Data Flow Tracking for Injection Attack Detection,
    IEEE International Symposium on Pacific Rim Dependable Computing (PRDC 2006), pp. 165—172 (2006).

Journals
  1. Susumu Mashimo, Ryota Shioya, and Koji Inoue:
    VMOR: Microarchitectural Support for Operand Access in an Interpreter,
    IEEE Computer Architecture Letters, (to appear).

  2. Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Bank-Aware Instruction Scheduler for a Multibanked Register File,
    IPSJ Journal of Information Processing, (to appear).

  3. Keita Doi, Ryota Shioya, and Hideki Ando:
    Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications,
    IPSJ Journal of Information Processing, Vol. 26, No. , pp. 445—460 (2018).

  4. Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Skewed Multistaged Multibanked Register File for Area and Energy Efficiency,
    IEICE Transactions on Information and Systems, Vol. E100-D, No. 4, pp. 822—837 (2017).

  5. Ushio Jimbo, Junji Yamada, Ryota Shioya, and Masahiro Goshima:
    Applying Razor Flip-Flops to SRAM Read Circuits,
    IEICE Transactions on Information and Systems, Vol. E100-C, No. 3, pp. 245—258 (2017).

  6. Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology,
    IEICE Transactions on Information and Systems, Vol. E100-C, No. 3, pp. 232—244 (2017).

  7. Ryota Shioya, Ryo Takami, Msahiro Goshima, and Hideki Ando:
    FXA: Executing Instructions in Front-End for Energy Efficiency,
    IEICE Transactions on Information and Systems, Vol. E99-D, No. 4, pp. 1092—1107 (2016).

  8. Ryota Shioya, and Hideki Ando:
    Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency,
    IEICE Transactions on Information and Systems, Vol. E99-D, No. 3, pp. 630—640 (2016).

  9. Hideki Ando, and Ryota Shioya:
    Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control,
    IEICE Transactions on Information and Systems, Vol. E99-D, No. 2, pp. 341—350 (2015).

  10. Naruki Kurata, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Address Order Violation Detection with Parallel Counting Bloom Filters,
    IEICE Transactions on Information and Systems, Vol. E98-C, No. 7, pp. 580—593 (2015).

  11. Ryota Shioya, Naruki Kurata, Takashi Toyoshima, Masahiro Goshima, and Shuichi Sakai:
    Register Indirect Jump Target Forwarding,
    IEICE Transactions on Information and Systems, Vol. E96-D, No. 2, pp. 278—288 (2013).
    DOI: 10.1587/transinf.E96.D.278
    [ PDF ]

  12. Shuji Yoshida, Soichiro Hirohata, Naruki Kurata, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    A Clocking Scheme Enabling Dynamic Time Borrowing,
    IPSJ Trans. on Advanced Computing Systems, Vol. 6, No. 1, pp. 1—16 (2013).
    (in Japanese)

  13. Masahiro Goshima, Naruki Kurata, Ryota Shioya, and Shuichi Sakai:
    Timing-Fault-Tolerant Out-of-Order Processor,
    IPSJ Trans. on Advanced Computing Systems, Vol. 6, No. 1, pp. 17—30 (2013).
    (in Japanese)

  14. Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, and Shuichi Sakai:
    Low-Overhead Architecture for Security Tag,
    IEICE Transactions on Information and Systems, Vol. E94-D, No. 1, pp. 69—78 (2011).
    DOI: 10.1587/transinf.E94.D.69

  15. Hironori Ichibayashi, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    Anti-Dualflow Architecture,
    IPSJ Trans. on Advanced Computing Systems, Vol. 1, No. 2, pp. 22—33 (2008).
    (in Japanese)

  16. Satoshi Katsunuma, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    SWIFT: String-Wise Information Flow Tracking,
    IPSJ Trans. on Advanced Computing Systems, Vol. 1, No. 2, pp. 261—274 (2008).
    (in Japanese)

  17. Ryota Shioya, Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    LRU-based Global Replacement Algorithm for Non-Uniform Shared Cache of Multi-Core Processors,
    IPSJ Trans. on Advanced Computing Systems, Vol. 48, No. SIG3, pp. 59—74 (2007).
    (in Japanese)

Domestic Symposiums (with peer review)
  1. Satoshi Arima, Naruki Kurata, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Timing-Fault-Tolerant Out-of-Order Processor,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2012,  pp. 270—279  (2012).
    (in Japanese)

  2. Mitsuo Date, Naruki Kurata, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Processor Architecture that Minimizes Register Renaming and Dispatch Network Authors,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2012,  pp. 280—288  (2012).
    (in Japanese)

  3. Takanori Inagaki, Ryota Shioya, and Hideki Ando:
    Simplifying the Load/Store Queue in the Virtual Reorder Buffer Scheme,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2012,  pp. 262—269  (2012).
    (in Japanese)

  4. Yuhei Horibe, Shinobu Miwa, Ryota Shioya, Masahiro Goshima, and Hironori Nakajo:
    Selective Cache Line Allocation with Load/Store Instruction Address,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2011,  pp. 316—323  (2011).
    (in Japanese)

  5. Yuji Ito, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Transactional Memory Selecting the Optimal Rollback Point,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2011,  pp. 324—331  (2011).
    (in Japanese)

  6. Naruki Kurata, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Improvement and Evaluation of Switch-on-Future-Event Multithreading,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2011,  pp. 82—91  (2011).
    (in Japanese)

  7. Hiroshi Toi, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Yet Another Taint Mode for PHP,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2011,  pp. 160—169  (2011).

  8. Ryota Shioya, Naruki Kurata, Jun Nakashima, Masahiro Goshima, and Shuichi Sakai:
    Switch-on-Future-Event Multithreading,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2010,  pp. 157—165  (2010).
    (in Japanese)

  9. Kazuo Horio, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Design of Area-Efficient Processor,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2010,  pp. 339—346  (2010).
    (in Japanese)

  10. Takanobu Kita, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    A Clocking Scheme with Relaxed Timing Constraints,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2010,  pp. 347—354  (2010).
    (in Japanese)

  11. Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    Area-Oriented Register Cache,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2008,  pp. 229—236  (2008).
    (in Japanese)

  12. Hironori Ichibayashi, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    Anti-Dualflow Architecture,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2008,  pp. 245—254  (2008).
    (in Japanese)

  13. Satoshi Katsunuma, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    SWIFT: String-Wise Information Flow Tracking,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2008,  pp. 167—176  (2008).
    (in Japanese)

  14. Daewung Kim, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    Low-overhead tagged architecture for variable-length tag,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2008,  pp. 177—185  (2008).
    (in Japanese)

  15. Kentaro Hara, Ryota Shioya, and Kenjiro Taura:
    Comparing Performance of General Purpose Processors with Memory Access Optimizations and the Cell -A Case Study with Cell Speed Challenge-,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2008,  pp. 157—166  (2008).
    (in Japanese)

  16. Ryota Shioya, Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    LRU-based Global Replacement Algorithm for Non-Uniform Shared Cache of Multi-Core Processors,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2006, Vol. 2006, No. 5,  pp. 23—31  (2006).
    (in Japanese)

  17. Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    Data Flow Tracking Based on Address Offset for Injection Attack Detection,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2006, Vol. 2006, No. 5,  pp. 515—524  (2006).
    (in Japanese)

Oral Presentations
  1. Shuji Yoshida, Satoshi Arima, Naruki Kurata, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Preliminary Experiment of A Clocking Scheme Enabling Dynamic Time Borrowing,
    IEICE Technical Reports CPSY2011–11,  pp. 13—18  (2011).
    (in Japanese)

  2. Kaoru Hayakawa, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Partial Platform Attestation,
    IEICE Technical Reports CPSY2011–11,  pp. 19—24  (2011).
    (in Japanese)

  3. Satoshi Arima, Takashi Okada, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Transient-Fault-Tolerant Out-of-Order Superscalar Processor,
    IEICE Technical Reports CPSY 2011-5, Vol. 5,  pp. 23—28  (2011).
    (in Japanese)

  4. Takashi Okada, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Evaluation of Fault-tolerant FPGA Architecture,
    The 73th National Convention of IPSJ, Vol. 1,  pp. 51—52  (2011).
    (in Japanese)

  5. Mitsuo Date, Naruki Kurata, Yuji Ito, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Dispatched Image Cache,
    The 73th National Convention of IPSJ, Vol. 1,  pp. 67—68  (2011).
    (in Japanese)

  6. Yuji Ito, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Transactional Memory Selecting the Optimal Checkpoint,
    The 73th National Convention of IPSJ, Vol. 1,  pp. 69—70  (2011).
    (in Japanese)

  7. Shuji Yoshida, Satoshi Arima, Takashi Okada, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    A Clocking Scheme Enabling Dynamic Time Borrowing,
    The 73rd National Convention of IPSJ, Vol. 1,  pp. 91—92  (2011).
    (in Japanese)

  8. Kaoru Hayakawa, Hiroshi Toi, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Partial Platform Attestation,
    The 73rd National Convention of IPSJ, Vol. 1,  pp. 91—92  (2011).
    (in Japanese)

  9. Yuhei Horibe, Shinobu Miwa, Ryota Shioya, Masahiro Goshima, and Hironori Nakajo:
    Selective Cache Allocation: Efficient Cache Management in a Multi-threaded Environment,
    IPSJ SIG Technical Report 2010-ARC-190, No. 1,  pp. 1—8  (2010).
    (in Japanese)

  10. Yuji Ito, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Transactional Memory Selecting the Optimal Rollback Point,
    IPSJ SIG Technical Report 2010-ARC-190, No. 9,  pp. 1—9  (2010).
    (in Japanese)

  11. Satoshi Arima, Takashi Okada, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Commit Scheme for Transient-Fault-Tolerant Out-of-Order Superscalar Processors,
    IPSJ SIG Technical Report 2010-ARC-190, No. 10,  pp. 1—10  (2010).
    (in Japanese)

  12. Naruki Kurata, Ryota Shioya, Jun Nakashima, Masahiro Goshima, and Shuichi Sakai:
    An Improvement of Switch-on-Future-Event Multithreading,
    IPSJ SIG Technical Report 2010-ARC-190, No. 27,  pp. 1—9  (2010).

  13. Hiroshi Toi, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Implementation and Evaluation of String-Wise Information Flow Tracking to PHP,
    IPSJ SIG Technical Report 2010-OS-115, No. 4,  pp. 1—11  (2010).
    (in Japanese)

  14. Takashi Okada, Takanobu Kita, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Fault-tolerant FPGA Architecture,
    IEICE Technical Reports CPSY 2010, Vol. 1,  pp. 221—222  (2010).
    (in Japanese)

  15. Satoshi Arima, Takashi Okada, Takanobu Kita, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Improvement of Transient-Fault-Tolerant Scheme for Out-of-Order Superscalar Processors,
    IEICE Technical Reports CPSY 2010, Vol. 1,  pp. 223—224  (2010).
    (in Japanese)

  16. Takanobu Kita, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    A proposal of a clocking scheme with relaxed timing constraints,
    The 72th National Convention of IPSJ, Vol. 1,  pp. 239—240  (2010).
    (in Japanese)

  17. Shuhei Eguchi, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    The effect of main memory bandwidth on processor performance,
    The 72th National Convention of IPSJ, Vol. 1,  pp. 179—180  (2010).
    (in Japanese)

  18. Kazuo Horio, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Design and implementation of Area-efficient superscalar processor,
    The 72th National Convention of IPSJ, Vol. 1,  pp. 181—182  (2010).
    (in Japanese)

  19. Yuki Yokota, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    A Platform for Preventing Information Leakage,
    The 72th National Convention of IPSJ, Vol. 3,  pp. 629—630  (2010).
    (in Japanese)

  20. Yen-chun Wang, Kazuo Horio, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Reevaluating the Renamed Trace Cache Architecture,
    The 72th National Convention of IPSJ, Vol. 1,  pp. 191—192  (2010).
    (in Japanese)

  21. Youngkwang Moon, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Platforms Attestation for Preventing Information Leakage,
    The 72th National Convention of IPSJ, Vol. 3,  pp. 632—633  (2010).
    (in Japanese)

  22. Yuji Ito, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Evaluation of Nested Transactional Memory Selecting the Optimal Rollback point,
    The 72th National Convention of IPSJ, Vol. 1,  pp. 187—188  (2010).
    (in Japanese)

  23. Naruki Kurata, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Improvement of Branch Pre-Decision on Loop Structure,
    The 72th National Convention of IPSJ, Vol. 1,  pp. 213—214  (2010).
    (in Japanese)

  24. Satoshi Arima, Takashi Okada, Kazuo Horio, Takanobu Kita, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Evaluation of Transient-Fault-Tolerant Scheme for Out-of-Order Superscalar Processors,
    The 72th National Convention of IPSJ, Vol. 1,  pp. 223—224  (2010).
    (in Japanese)

  25. Hiroshi Toi, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Implementation of String-Wise Information Flow Tracking to PHP,
    The 72th National Convention of IPSJ, Vol. 3,  pp. 623—624  (2010).
    (in Japanese)

  26. Youngkwang Moon Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Platforms Attestation for Preventing Information Leakage,
    IEICE Technical Reports CPSY 2009,  pp. 13—18  (2009).
    (in Japanese)

  27. Yuki Yokota, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    A Platform for Preventing Information Leakage,
    IEICE Technical Reports CPSY 2009,  pp. 7—12  (2009).
    (in Japanese)

  28. Yuji Ito, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Nested Transactional Memory Selecting the Optimal Rollback Point,
    IPSJ SIG Technical Report 2009-ARC-184, No. 5,  pp. 1—11  (2009).
    (in Japanese)

  29. Kazuo Horio, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Design of Area-efficient Processor,
    IPSJ SIG Technical Report 2009-ARC-184, No. 27,  pp. 1—7  (2009).
    (in Japanese)

  30. Takanobu Kita, Sho Tarui, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Exploratory evaluation of a clocking scheme with relaxed timing constraints,
    IEICE Technical Reports CPSY 2009,  pp. 61—66  (2009).
    (in Japanese)

  31. Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Branch Pre-Decision,
    IPSJ SIG Technical Report 2008-ARC-179,  pp. 67—72  (2008).
    (in Japanese)

  32. Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    Evaluation of Area-Oriented Register Cache,
    IPSJ SIG Technical Report 2008-ARC-178,  pp. 13—18  (2008).
    (in Japanese)

  33. Toru Ando, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Dynamic Helper Threading Based on Loop Structure,
    IPSJ SIG Technical Report 2008-ARC-179,  pp. 139—144  (2008).
    (in Japanese)

  34. Shuhei Eguchi, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    The effect of main memory bandwidth on processor performance,
    IPSJ SIG Technical Report 2008-ARC-180,  pp. 15—20  (2008).
    (in Japanese)

  35. Kazuo Horio, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Evaluation of Twintail Architecture,
    IPSJ SIG Technical Report 2008-ARC-179,  pp. 7—12  (2008).
    (in Japanese)

  36. Sho Tarui, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    A Timing-Fault-Tolerant Clocking Scheme,
    IEICE Technical Reports CPSY 2008-14,  pp. 25—30  (2008).
    (in Japanese)

  37. Satoshi Katsunuma, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    String-Aware Information Flow Tracking to Detect Injection Attacks,
    IEICE Technical Report CPSY2007–84,  pp. 25—30  (2008).
    (in Japanese)

  38. Takanobu Kita, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    Speculation scheme that continues executing mispredicted instructions,
    IPSJ SIG Technical Report 2008-ARC-178,  pp. 7—12  (2008).
    (in Japanese)

  39. Yuki Yokota, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    Implicit Information Flow Tracking for Preventing Information Leakage,
    The 70th National Convention of IPSJ,  pp. 111—112  (2008).
    (in Japanese)

  40. Hidetsugu Irie, Ken Sugimoto, Ryota Shioya, Kenichi Watanabe, Masahiro Goshima, and Shuichi Sakai:
    A Lightweight Write Error Detection for Register-file Using Improved Passive WAB,
    IEICE Technical Reports CPSY 2008-3,  pp. 13—18  (2008).
    (in Japanese)

  41. Hiroyuki Kurita, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, and Shuichi Sakai:
    Dynamic Information Flow Control for Preventing Information Leakage,
    IPSJ SIG Technical Report 2007-ARC-172, Vol. 2007, No. 17,  pp. 227—232  (2007).
    (in Japanese)

Poster
  1. Ushio Jimbo, Ryota Shioya, and and Masahiro Goshima:
    Clocking Scheme That Realizes Ballistic Signal Flow,
    IEEE/ACM International Symposium on Microarchitecture (MICRO 51) Student Research Competition,  (2018).

  2. Reoma Matsuo, Ryota Shioya, and Hideki Ando:
    Improving Instruction Fetch Throughput with Dynamic Control of Pipeline Structure,
    IEEE/ACM International Symposium on Microarchitecture (MICRO 51) Student Research Competition,  (2018).

  3. Tomoki Tajimi, Yuki Futamase, Masaki Hayashi, Ryota Shioya, Masahiro Goshima, and Tomoaki Tsumura:
    Speculatively Granting Conflicting Accesses on Hardware Transactional Memory,
    IEEE/ACM International Symposium on Microarchitecture (MICRO 51) Student Research Competition,  (2018).

  4. Hiroshi Toi, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Yet Another Taint Mode for PHP,
    IEEE International Symposium on Pacific Rim Dependable Computing (PRDC 2010),  (2010).

  5. Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    Design and Implementation of a Processor Simulator 'Onikiri2',
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2009,  pp. 120—121  (2009).
    (in Japanese)

  6. Shuhei Eguchi, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    The effect of main memory bandwidth on processor performance,
    Symp. on Advanced Computing Systems and Infrastructures (SACSIS) 2009,  pp. 147—148  (2009).
    (in Japanese)

  7. Li Kunbo, Ryota Shioya, Masahiro Goshima, and Shuichi Sakai:
    String-Wise Information Flow Tracking,
    STARC Forum/Symposium,  (2008).
    (in Japanese)